introduction the ADC3214 is a 14-bit, 1 mhz a/d converter with a built-in sample- and-hold amplifier. it was designed for use in applications requiring high speed and high resolution front ends, such as ate, medical imaging, radar, communications, and analytical instrumentation. the ADC3214 is a cost-effective solution for both time and frequency domain applications. it is capable of digitizing a 500 khz signal at a 1 mhz rate with a guarantee of no missing codes. signal-to-noise ratio is 76 db at input frequencies from dc to 100 khz. with a 1 mhz sampling rate and a full-scale step re- sponse to 14-bit accuracy of one conversion, this sampling a/d converter is ideally suited for applications with multiplexed signal sources. the ADC3214 utilizes the latest surface-mount technologies to produce a cost-effective, high-performance part in a 2" x 3" fully shielded package. it is designed around a two-pass, subranging architecture that integrates a low distortion sample-and-hold amplifier, precision voltage reference, all the necessary timing circuitry and tri-state cmos/ttl-compatible out- puts for ease of system integration. features q 14-bit resolution q 1 mhz throughput rate q reduced cost q reduced size q no missing codes: 0? to +60? q signal-to-noise ratio: 76 db q peak distortion: ?2 db @ 100 khz q total harmonic distortion: ?0 db @ 100 khz q ease of use q built-in s/h amplifier q ttl compatibility q high input impedance (100 m ) applications q radar q analytical instrumentation q spectroscopy q digital telecommunications q automatic test equipment q high-resolution imaging q medical data acquisition q multiplexed data acquisition figure 1. ADC3214 functional block diagram. high speed, 14-bit, 1 mhz, sampling a/d converter with built-in sample-and-hold amplifier ADC3214 b1-b14 o/u flow s/h amplifier scaling & offset circuit ref. ckt. 4-bit linear dac 8-bit adc signal in range 1 range 2 s/h out a/d in ext. off adj. ext. gain adj. +ref. out trigger enable ref. ref. adc clk. p2 p1 l o g i c +15v ana. rtn. ?5v +5v dig. rtn. eoc ? continued on page 3.
analog input input range 1.25v, ?.5v input bias current 5 na max. s/h input capacitance 10 pf typ. s/h input resistance 100 m min. a/d input resistance 1.25 k to ground digital inputs compatibility cmos, ttl logic levels logic ? ?.5v min., 0.8v max. logic ? 2.0v min., 5.5v max. trigger negative edge triggered loading 1 ttl load pulse width 210 ns min., 390 ns max. output enable active low; b1-b14, o/u flow propagation delay 50 ns max. digital outputs maximum output drive ? ma min. logic levels logic ? 0v min., +0.4v max. logic ? +3.5v min., 5.0v max. output coding parallel data, offset binary eoc falling edge, data valid 20 ns prior to falling edge over/under flow active high; 1/2 code below fs internal reference voltage 10.0v typ. stability 15 ppm/? typ. available current 2 1 ma max. dynamic characteristics maximum throughput rate 1 mhz min. a/d conversion time 600 ns max. s/h aperture delay 10 ns typ. s/h aperture jitter 15 ps rms typ., 30 ps rms max. s/h feedthrough 3 ?4 db typ., ?0 db max. full power bandwidth 1.5 mhz min., 2.5 mhz typ. small signal bandwidth 3.5 mhz typ. signal to noise ratio 4 76 db min., 78 db typ. peak distortion 5 10 khz ?6 db max., ?5 db typ. 100 khz ?2 db max., ?9 db typ. 540 khz ?6 db typ. total harmonic distortion 6 10 khz ?4 db max. 100 khz ?0 db max. 540 khz ?4 db typ. step response 7 400 ns to ?.01% 500 ns to ?.006% transfer characteristics resolution 14 bits quantization error ?.5 lsb relative accuracy ?.006% fsr max. differential non-linearity ?.75 lsb @ 25?, 1 lsb from 0 c to 60? monotonicity guaranteed no missing codes guaranteed from 0 c to 60? offset error 8 ? mv max. gain error 8 ?.1% fsr max. noise 9 180 ? rms typ., 266 ? rms max. stability (0? to 60?) differential non-linearity 1 ppm fsr/? max. offset voltage 100 ?/? max. gain ?5 ppm fsr/? max. warm-up time 10 minutes 15v supply rejection 15 ppm fsr/% change max. offset 15 ppm fsr/% change max. gain 15 ppm fsr/% change max. +5v supply rejection offset ?0 ppm fsr/% change max. gain ?0 ppm fsr/% change max. power requirements 10 15v supplies 14.25v min., 15.75v max. +5v supply +4.75v min., +5.25v max. +15v current drain 48 ma typ. ?5v current drain 63 ma typ. +5v current drain 132 ma typ. power consumption 2.35w typ. environmental & mechanical temperature range rated performance 0? to 60? storage ?5? to 75? relative humidity (non-condensing) 0 to 85% to 60? dimensions 1.99?x 2.99?x 0.44? (50.5 x 75.9 x 11.2 mm) shielding electromagnetic 5 sides case potential ground ADC3214 specifications 1
notes 1. unless otherwise noted, all specifications apply at 25? ambient with power supplies of 15v and ?v. 2. external reference load to remain stable during conver- sion. 3. measured with a full scale step input with a 20v/? slew rate. 4. signal-to-noise ratio represents the ratio between the rms value of the signal and the total rms noise below the nyquist rate. the total rms noise is computed by: (1) sum- ming the noise power in all frequency bins not correlated with the test signal; (2) estimating the total noise power contained in all harmonic frequency bins; and (3) comput- ing the rms noise from the sum of (1) and (2). 5. peak distortion represents the ratio between the highest spurious frequency component below the nyquist rate and the signal. note that in computing peak distortion the esti- mated noise allocated to the harmonic frequency bins in computing snr is first removed. see note 4. 6. total harmonic distortion represents the ratio between the rms sum of all harmonics up to the 100th harmonic and the rms value of the signal. note that in computing total harmonic distortion, the estimated noise allocated to the harmonic frequency bins in computing snr is first re- moved. see note 4. 7. step response represents the time required to achieve the specified accuracies after a full scale step change at the signal input, specified at a 1 mhz throughput rate. 8. externally adjustable to zero. see coding and trim proce- dure. 9. thermal noise from the s/h and a/d converter, not includ- ing quantization noise. 10. analogic highly recommends the use of linear power sup- plies with its high performance, high resolution a/d con- verters. however, if system requirements provide only a +5v supply and limited space, the use of the analogic sp7015 dc-to-dc converter will provide a low noise solu- tion which will not degrade the ADC3214 performance. specifications subject to change without notice. superior performance and ease-of-use make the ADC3214 the ideal solution for applications requiring a sample-and-hold amplifier directly at the input to the a/d converter. having the s/h amplifier integrated with the a/d converter benefits the system designer in two ways. first, the s/h has been designed specifically to comple- ment the performance of the a/d converter; for exam- ple, the acquisition time, hold mode settling and droop rate have been optimized for the a/d converter, resulting in exceptional overall performance. second, the design- er achieves true 14-bit performance, avoiding degrada- tion due to ground loops, signal coupling, jitter and digi- tal noise introduced when separate s/h and a/d con- vertesr are interconnected. furthermore, the accuracy, speed, and quality of the ADC3214 are fully ensured by thorough, computer-controlled factory tests of each unit. ADC3214 specifications coding and trim procedure refer to figures 2 and 3 for the ADC3214 coding and trim procedure. figure 2 shows the external offset and gain adjust configuration. figure 3 shows the output offset binary coding of the ADC3214 a/d converter. the voltages mentioned in the following trim procedure refer to the ?.5v input range with the num- bers in parentheses referring to the 1.25v input range. to trim the offset of the ADC3214, apply ?53 ? (?6 ?) to the analog input. adjust the external offset trim potentiometer such that each of the 14 bits alternates equally between ??and ?? using the setup as de- scribed in figure 2, the sensitivity of the offset adjust- ment is typically 6 lsbs per volt. to trim the gain of the ADC3214, apply +2.499542v (+1.249771v) to the analog input and adjust the exter- nal gain trim potentiometer such that the 13 msbs are ??and the lsb alternates equally between ??and ?? using the setup as described in figure 2, the sensitivi- ty of the gain adjustment is typically 0.14% per volt. timing considerations the timing diagram in figure 4 shows the timing char- acteristics of the ADC3214 a/d converter. upon a high-to-low transition of the trigger input, the internal logic of the ADC3214 places the input s/h amplifier (see figure 1) into the hold mode. approximately 550 ns after trigger, the internal s/h amplifier returns to the sample mode to begin acquiring the next sample. offset adjustment gain adjustment ?5v +15v ext. off. adj. 1 3 7 50 k ana. rtn. ext. gain adj. +ref. out 2 4 6 10 k figure 2. external offset and gain adjust configuration. analog input digital output 1.25v ?.5v msb lsb 11111111111111 = +1.24985v +2.49970v 10000000000000 = 0.00000v 0.00000v 00000000000000 = 1.25000v ?.50000v b1,b2 .....b14 = pin label figure 3. output coding for the ADC3214. continued from page 1.
approximately 200 ns later (750 ns elapsed time), the a/d converter has completed the conversion process and latches the data into the output tri-state latches. the data is valid 20 ns prior to the high-to-low transi- tion of the eoc pulse. layout considerations the high resolution of the ADC3214 a/d converter makes it necessary to pay careful attention to the print- ed circuit layout for the device. it is, for example, im- portant to separate analog and digital grounds and to return them separately to the system power supply. digital grounds are often noisy or ?litchy,?and these glitches can have adverse effects on the performance of the ADC3214 if they are introduced to the analog portions of the a/d converter s circuitry. at 14-bit reso- lution, the size of the voltage step between one code transition and the succeeding one is only 152 ? (305 ? for the ?.5v range), so it is evident that any noise in the analog ground return can result in erroneous or missing codes. it is therefore important to configure a low-impedance ground-plane return on the printed-cir- cuit board. this is the point where the analog and digital returns should be made common, not at the supplies. principles of operation to understand the operating principles of the ADC3214 a/d converter, refer to figures 4 and 7. the simplified block diagram of figure 7 illustrates the two succes- sive passes in the sub-ranging conversion scheme of the ADC3214. the ADC3214 is a 14-bit sampling a/d converter with throughput rates to 1 mhz. it has two externally config- urable input ranges of 1.25v and ?.5v. this is easily accomplished by externally connecting pins 15 and 16 for the 1.25v range and leaving both pins open (n/c) for the ?.5 range (see figure 5). the s/h amplifier has a gain of x? or x?, providing an output of ?.5v regardless of the input. this simplifies the calibration of the adc by reducing the required gain of the summing amplifier. the first pass starts at a high-to-low transition of the trigger pulse. this signal places the s/h into the hold mode and starts the timing logic. in the first pass, the output of the s/h is attenuated by a factor of 0.4 and offset to convert the 5v full scale adc range to the 2v full scale range of the flash adc. after approximately 110 ns, the attenuator circuitry has settled to 9-bit ac- curacy at which time the adc digitizes the first pass. the 8 bits take two paths: to the internal logic and to the 8 most significant bits of a 14-bit accurate d/a con- verter, setting up the second pass. 1. ?5v 38. dig rtn 2. ana rtn 37. +5v 3. +15v 36. o/u range 4. ext range adj 35. bit 1 (msb) 5. ref rtn 34. bit 2 6. +v ref out 33. bit 3 7. ext offs adj 32. bit 4 8. s/h ana out 31. bit 5 9. adc in 31. bit 6 10. no pin 29. bit 7 11. no pin 28. bit 8 12. ana rtn 27. bit 9 13. signal in 26. bit 10 14. do not connect 25. bit 11 15. range 2 24. bit 12 16. range 1 23. bit 13 17. do not connect 22. bit 14 18. ana rtn 21. out enable 19. trigger 20. eoc connect pin 8 to pin 9. figure 5. ADC3214 pin assignments. 0.100" top view 1.800" typ. 1.990" max. 2.990" max. 2.800" typ. 0.015" min. 0.095" max. 0.095" max. 0.440" max. side view recommended hole size: 0.035 pin diameter: 0.020 typical pin length: 0.125" to 0.250" 138 19 20 figure 6. ADC3214 mechanical. aaa aaa aaa aaa n n+1 20 ns n n? 0 550 750 1000 trigger s/h cont. (int.) data valid timing (ns) eoc figure 4. ADC3214 timing diagram.
in the second pass, the output of the d/a converter is subtracted from the output of the s/h amplifier. the nominal error voltage of ?.5 lsb (at the 8-bit level it is 5v/256 or 19.5 mv) is amplified by 25.6 to achieve 1/4 full scale range of the flash adc, thus allowing a 2-bit overlap safety margin. the effective resolution there- fore becomes the digital summation of two 8-bit results with the 2 lsbs of pass 1 overlapping the 2 msbs of pass 2. at approximately 550 ns after trigger, the error signal has settled to 14-bit accuracy and the adc then digitizes the second pass. the internal logic then places the s/h back into the sample mode to begin acquiring the next sample. the second pass data is latched into the output tri-state registers and the con- version is now complete. this is marked by a high-to- low transition of the eoc pulse with the data valid 20 ns prior to eoc. the ADC3214 has a tri-state output structure. users can enable the fourteen data bits and the overflow/underflow bit with the enable pin. this fea- ture makes it possible to transfer data from the ADC3214 to a microprocessor bus. however, to pre- vent the coupling of high frequency noise from the mi- croprocessor bus into the a/d converter, the output data must be buffered (see figure 8). the 1/4 full scale range, or 2-bit overlap in the second pass, is a scheme used in the ADC3214 to provide an output word that is accurate and linear to 14 bits. this method corrects for gain and linearity errors in the am- plifying circuitry, as well as the 8-bit flash a/d convert- er. without the use of this overlapping correction scheme, it would be necessary that all the components in the ADC3214 be accurate to the 14-bit level. while such a design might be possible to realize on a labora- tory benchtop, it clearly would be impractical to achieve on a production basis. the key to the conver- sion technique used in the ADC3214 is the 14-bit ac- curate and 14-bit linear d/a converter, which serves as the reference element for the conversion s second pass. the use of proprietary sub-ranging architecture in the ADC3214 results in a sampling a/d converter that offers unprecedented speed and transfer charac- teristics at the 14-bit level. 8-bit adc analog input s/h amplifier scaling & offset circuit x0.4 aaa aaa aaa aaa aaa aaa aaa overlap logic aaa aaa aaa aaa aaa aaa 8-bit adc to summing amp for 2nd pass 2v p-p 1st pass from s/h out 2nd pass x25.6 0.5v p-p 14-bit linear dac logic b1-b14 o/u 8 msbs from 1st pass logic to 14-bit dac for 2nd pass ? figure 7. simplified block diagram.
typical application figure 8 shows a typical application circuit for the ADC3214-m a/d converter: an eight channel, high resolution, high speed data acquisition system. this circuit could be part of an automatic test system or the front end of a data acquisition and control system. the 14-bit resolution of the ADC3214 provides 84 db dynamic range for each channel, and the 1 mhz throughput rate provides approximately 125 khz throughput per channel. for interfacing with a microprocessor-driven 16-bit bus, the use of digital buffers may be required to prevent coupling of high frequency noise from the microproces- sor bus into the a/d converter. note that in figure 8, the signal return is not tied to the ground-plane return but instead is common at a strategic point inside the ADC3214. the ability of the ADC3214 sample-and-hold amplifier to acquire new data to within 1 lsb after a full-scale step change at the analog input and the superb dc characteristics exhibited by the ADC3214 are the key factors in establishing this part as the ideal choice for high speed data acquisition systems. ordering guide simply specify: ADC3214m 14-bit sampling a/d converter sp7015 dc-to-dc converter +15v ?5v ana rtn sig rtn sig in s/h out adc in range 1 range 2 en trig eoc dig rtn +5v o/v b1 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 ADC3214 8:1 mux ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 sig rtn digital buffer 15 10 ? .01 +5v dig rtn 6.8 ? .01 6.8 ? .01 ana rtn ?5v +15v logic 3 trig figure 8. ADC3214-m typical application and connection.
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